Trademark: 88423409
Status Date
Monday, November 22, 2021
Filing Date
Thursday, May 9, 2019
Published for Opposition
Tuesday, February 25, 2020
Abandoned Date
Monday, November 22, 2021
9 Integrated circuit (IP) cores implementing embedded field programmable gate arrays (FPGAs) with clusters of multiplier-accumulators (MACs) optimized for neural network inference; downloadable software for programming the embedded field programmable gate array (FPGA) integrated circuit (IP) cores using neural network description models; instructional documentation and user guides, sold as a unit, for use with the foregoing
NEURAL NETWORK MAXIMUM; NEURAL NETWORK MAX
Nov 22, 2021
Abandonment Notice E-Mailed - No Use Statement Filed
Nov 22, 2021
Abandonment - No Use Statement Filed
Apr 22, 2021
Notice Of Approval Of Extension Request E-Mailed
Apr 20, 2021
Extension 2 Granted
Apr 20, 2021
Extension 2 Filed
Apr 20, 2021
Teas Extension Received
Oct 21, 2020
Notice Of Approval Of Extension Request E-Mailed
Oct 19, 2020
Extension 1 Granted
Oct 19, 2020
Extension 1 Filed
Oct 19, 2020
Teas Extension Received
Apr 21, 2020
Noa E-Mailed - Sou Required From Applicant
Feb 25, 2020
Official Gazette Publication Confirmation E-Mailed
Feb 25, 2020
Published For Opposition
Feb 5, 2020
Notification Of Notice Of Publication E-Mailed
Jan 22, 2020
Approved For Pub - Principal Register
Jan 22, 2020
Teas/Email Correspondence Entered
Jan 22, 2020
Correspondence Received In Law Office
Jan 20, 2020
Assigned To Lie
Jan 7, 2020
Teas Response To Office Action Received
Jul 19, 2019
Notification Of Non-Final Action E-Mailed
Jul 19, 2019
Non-Final Action E-Mailed
Jul 19, 2019
Non-Final Action Written
Jul 15, 2019
Assigned To Examiner
May 29, 2019
New Application Office Supplied Data Entered In Tram
May 13, 2019
New Application Entered In Tram
Trademark Alertz updated from USPTO on 2030-01-24
