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Trademark: 78195575
Status Date
Thursday, June 24, 2004
Filing Date
Tuesday, December 17, 2002
Published for Opposition
Tuesday, September 30, 2003
Abandoned Date
Thursday, June 24, 2004
9 Capital equipment for the semiconductor manufacturing industry, namely, inspection and test apparatus, namely, Integrated Circuit (IC) design verification, debug, and failure analysis systems; automated test equipment (ATE); backside device imaging; photon timing systems; temperature mapping systems; and emission detection systems, all for measuring the performance characteristics of semiconductors
Sep 2, 2004
Abandonment - No Use Statement Filed
Dec 23, 2003
Noa Mailed - Sou Required From Applicant
Sep 30, 2003
Published For Opposition
Sep 10, 2003
Notice Of Publication
Aug 9, 2003
Approved For Pub - Principal Register
Jul 5, 2003
Correspondence Received In Law Office
Jul 15, 2003
Case File In Ticrs
Jul 5, 2003
Teas Response To Office Action Received
Jul 3, 2003
Non-Final Action E-Mailed
Jun 17, 2003
Assigned To Examiner
Trademark Alertz updated from USPTO on 2030-01-24