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Trademark: 77546260
Status Date
Friday, August 21, 2009
Filing Date
Wednesday, August 13, 2008
Abandoned Date
Thursday, May 21, 2009
9 Electronic Design Automation software for linting and design rule checking VHDL and Verilog hardware description language (HOL) designs
Aug 21, 2009
Abandonment Notice Mailed - Incomplete Response
Aug 21, 2009
Abandonment - Incomplete Response
Jan 8, 2009
Notification Of Notice Of Unresponsive Amendment - E-Mailed
Jan 8, 2009
Notice Of Unresponsive Amendment - E-Mailed
Jan 8, 2009
Report Unresponsive Amendment - Completed
Dec 20, 2008
Amendment From Applicant Entered
Dec 20, 2008
Correspondence Received In Law Office
Dec 20, 2008
Assigned To Lie
Dec 8, 2008
Paper Received
Nov 20, 2008
Notification Of Non-Final Action E-Mailed
Nov 20, 2008
Non-Final Action E-Mailed
Nov 20, 2008
Non-Final Action Written
Nov 20, 2008
Assigned To Examiner
Aug 19, 2008
Notice Of Pseudo Mark Mailed
Aug 18, 2008
New Application Entered In Tram
Trademark Alertz updated from USPTO on 2030-01-24