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Trademark: 77546228
Status Date
Friday, June 26, 2009
Filing Date
Wednesday, August 13, 2008
Abandoned Date
Thursday, May 21, 2009
9 Electronic Design Automation (EDA) product for hardware assisted simulation of VHDL and Verilog hardware description language (HDL) designs. The product will co-simulate designs with software on event-by-event basis with RTL simulators. The hardware supports Windows, UNIX and Linux Operating Systems, based on a PCI interface
Jun 26, 2009
Abandonment Notice Mailed - Failure To Respond
Jun 26, 2009
Abandonment - Failure To Respond Or Late Response
Nov 20, 2008
Notification Of Non-Final Action E-Mailed
Nov 20, 2008
Non-Final Action E-Mailed
Nov 20, 2008
Non-Final Action Written
Nov 20, 2008
Assigned To Examiner
Aug 18, 2008
New Application Entered In Tram
Trademark Alertz updated from USPTO on 2030-01-24