Trademark: 75724206
Status Date
Friday, September 7, 2001
Filing Date
Tuesday, June 8, 1999
Published for Opposition
Tuesday, December 12, 2000
Abandoned Date
Friday, September 7, 2001
9 Test generator computer software for verification of electronic designs; computer software to simulate system operation of integrated circuit designs; computer software for use in RTL-level simulation to carry out random pattern test control functions on integrated circuit designs; and corresponding instructional manuals sold as a unit
Jan 4, 2002
Abandonment - No Use Statement Filed
Mar 6, 2001
Noa Mailed - Sou Required From Applicant
Dec 12, 2000
Published For Opposition
Nov 10, 2000
Notice Of Publication
Jul 21, 2000
Approved For Pub - Principal Register
Jun 29, 2000
Examiner's Amendment Mailed
Feb 16, 2000
Non-Final Action Mailed
Jan 27, 2000
Assigned To Examiner
Jan 10, 2000
Assigned To Examiner
Trademark Alertz updated from USPTO on 2030-01-24